Safety and Security: i960MX's distinctive strengths exploited using ICC Ada
Irvine Compiler Corporation offers programmers complete access to the unrivaled functionality of Intel's i960MX microprocessor. ICC Ada supports MX ''tagged mode,'' allowing hardware-enforcement of Ada's package and type boundaries. Programmers can partition software code and data into protected objects to facilitate safety or security verification. Choose the compiler for the reasons you chose the processor: performance and protection. Building from a foundation of solid tools and techniques ICC Ada/i960MX was validated in June of 1997. ICC has worked closely with its customers to provide the features and optimizations necessary to ensure project success. This commitment to customer satisfaction, combined with ICC's focus on avionics applications, has made ICC a leading supplier of Ada compilers for the i960 processor.
For development before target hardware is available: ICC's instruction-level simulator
Many projects get off to a difficult start because code cannot be developed, tested and integrated without prototype hardware. ICC's i960 simulator allows the user to code, debug and evaluate application programs before hardware is available. The simulator can be used in conjunction with the source level debugger and execution profiler (useful for locating application ''hot spots'' that require attention) and remains useful as a testing tool even after hardware is developed.
Assuring efficiency with ICC's optimization features
ICC's Ada/i960 compiler implements a wide range of Ada-oriented, classical and i960-specific optimizations. Both time and space optimizations are supported. The ICC Ada front-end and optimizer perform constant expression folding and propagation, static elaboration (including tasks), redundant check elimination, local variable lifetiming and registerization, value following, dead code elimination, subprogram inlining (both automatic and user- directed), common subexpression reduction and many other optimizations.
The i960 code generator maximizes execution performance by fully utilizing the i960 instruction set. In addition to optimized instruction selection based on the optimization mode and the specific i960 target type, it also contains both an instruction peepholer and code-scheduler to ensure high throughput. Optimizations specific to the i960 include optimized instruction and address mode selection, use of local and global registers with lifetiming and value following, subroutine frame registerization and elimination, i960 process-based tasking, parameter passing by registers and others.
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